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A low power low noise amplifier for a 128 channel detector read-out chip

Conference · · IEEE Trans. Nucl. Sci.; (United States)
OSTI ID:6080420
This paper describes the design of a low power, low noise CMOS amplifier. The amplifier was designed using the folded cascade configuration and was implemented on a 3 ..mu..m double polysilicon process. The amplifier is part of a 128 channel charge amplifier array chip for use in the read-out of radiation detectors with many channels. Aspects of the amplifier design such as bandwidth, pulse response, and noise are discussed and the effects of individual transistors are shown thereby relating circuit performance to process parameters; circuit test results are presented and radiation test results are included.
Research Organization:
Rutherford Appleton Lab., Chilton, Oxon, OX11 OQX (GB)
OSTI ID:
6080420
Report Number(s):
CONF-881103-
Conference Information:
Journal Name: IEEE Trans. Nucl. Sci.; (United States) Journal Volume: 36:1
Country of Publication:
United States
Language:
English