Testing programmable logic arrays by sum of syndromes

Journal Article · Tue Sep 01 04:00:00 EDT 1987 · IEEE Trans. Comput.; (United States)

DOI:https://doi.org/10.1109/TC.1987.5009540· OSTI ID:6079025

Serra, M; Muzio, J C

Syndrome testing is a simple and effective fault detection technique applicable to many general circuits. It is particularly useful in two-level circuits, such as programmable logic arrays (PLA's). For a multiple-output network, like PLA's, existing methods test the individual syndromes for each function, where a fault should be detectable in at least one output. This paper shows that the weighted sum of syndromes of all the outputs covers all single stuck-at-faults, bridging faults, and cross-point faults. Primary input faults are also covered except in one special case which requires some preventive design for testability. This results in the use of one test to cover all single faults.

• Research Organization: Dept. of Computer Science, Univ. of Victoria, Victoria, BC
• OSTI ID: 6079025
• Journal Information: IEEE Trans. Comput.; (United States), Journal Name: IEEE Trans. Comput.; (United States) Vol. C-36:9; ISSN ITCOB
• Country of Publication: United States
• Language: English

Related Subjects

42 ENGINEERING
420800 -- Engineering-- Electronic Circuits & Devices-- (-1989)
99 GENERAL AND MISCELLANEOUS
990210* -- Supercomputers-- (1987-1989)
ARRAY PROCESSORS
COMPUTERS
DESIGN
DIGITAL COMPUTERS
ELECTRONIC CIRCUITS
FAILURES
FAULT TOLERANT COMPUTERS
LOGIC CIRCUITS
PERFORMANCE TESTING
PROGRAMMING
TESTING