Fault detection in programmable logic arrays

Journal Article · Thu May 01 04:00:00 EDT 1986 · Proc. IEEE; (United States)

DOI:https://doi.org/10.1109/PROC.1986.13529· OSTI ID:5606871

Somenzi, F; Gai, S

When designing faul-tolerant systems including programmable logic arrays (PLAs), the various aspects of these circuits concerning fault diagnosis have to be taken into account. The peculiarity of these aspects, ranging from fault models to test generation algorithms and to self-checking structures, is due to the regularity of PLAs. The fault model generally accepted for PLAs is the crosspoint defect; it is employed by dedicated test generation algorithms, based on the fact that PLAs implement a two-level combinational function. The problem of accessing inputs and outputs of the PLA can be alleviated by augmenting the PLA itself so as to simplify the test vectors to be applied, making them function independent in the limit. A further step consists in the addition of the circuitry required to generate test vectors and to evaluate the answer, thus obtaining a built-in self-test (BIST) architecture. Finally, high reliability can be achieved with PLAs featuring concurrent error detection.

• Research Organization: SGC Microelettronica, Central R and D, Agrate Brianza (MI), I-20041
• OSTI ID: 5606871
• Journal Information: Proc. IEEE; (United States), Journal Name: Proc. IEEE; (United States) Vol. 74:5; ISSN IEEPA
• Country of Publication: United States
• Language: English

Related Subjects

42 ENGINEERING
420800 -- Engineering-- Electronic Circuits & Devices-- (-1989)
99 GENERAL AND MISCELLANEOUS
990200* -- Mathematics & Computers
ALGORITHMS
CIRCUIT THEORY
COMPUTERS
DESIGN
DIGITAL COMPUTERS
ELECTRONIC CIRCUITS
FAILURES
FAULT TOLERANT COMPUTERS
LOGIC CIRCUITS
MATHEMATICAL LOGIC
PROGRAMMING
TENSORS
TESTING
VECTORS