High voltage considerations for Silicon-on-Insulator devices using porous silicon

Conference · Sat Dec 31 23:00:00 EST 1988

DOI:https://doi.org/10.1149/198915.0344PV· OSTI ID:6001461

Guilinger, T. R.; Kelly, M. J.; Tsao, S. S.; Cristensen, T. M.; Schubert, W. K.

We describe a Silicon-on-Insulator (SOI) structure for high voltage BICMOS uniquely suited to the use of porous silicon (PS). In this SOI structure, bulk, high speed bipolar devices are readily integrated with CMOS high voltage and logic devices (smart power). To investigate the processing compatibility of PS with this structure, we measured breakdown strength and etch rate of thermally treated PS in 7:1 buffered oxide etch (BOE) and determined that they can approach values typical of thermal silicon oxides/nitrides. 7 refs., 2 figs.

• Research Organization: Sandia National Labs., Albuquerque, NM (USA)
• DOE Contract Number: AC04-76DP00789
• OSTI ID: 6001461
• Report Number(s): SAND-89-1282C; CONF-890518-3; ON: DE89013162
• Country of Publication: United States
• Language: English

Related Subjects

36 MATERIALS SCIENCE
360601* -- Other Materials-- Preparation & Manufacture
360603 -- Materials-- Properties
42 ENGINEERING
420800 -- Engineering-- Electronic Circuits & Devices-- (-1989)
CHALCOGENIDES
ELECTRICAL EQUIPMENT
ELECTRICAL INSULATORS
ELEMENTS
EQUIPMENT
FABRICATION
MATERIALS
NITRIDES
NITROGEN COMPOUNDS
OXIDES
OXYGEN COMPOUNDS
PNICTIDES
POROUS MATERIALS
SEMICONDUCTOR DEVICES
SEMIMETALS
SILICON