A BiCMOS front-end system with binary delay line for capacitive detector read-out
- Interuniversity Inst. for High Energies, Brussels (Belgium)
In the field of elementary particle physics, trajectories of charged particles are reconstructed from data obtained from tracking detectors. In the future large Hadron collider (LHC) accelerator at CERN, bunches of protons will collide every 25 ns. Large detector systems are constructed around the points of collision. These detectors often include smaller tracking subdetectors of different types like silicon, GaAs, or gaseous detectors--capacitive detectors that are read out by appropriate electronics located close to the collision region where the radiation levels are high. Here, as part of the entire readout chip, a low-power high-gain transresistance amplifier has been developed, followed by a high-speed, low-power small offset comparator and a binary delay line. The amplifier is balanced, fully differential in circuit topology, and symmetrical in layout, making it radiation tolerant and relatively insensitive to varying magnetic fields. Also, the comparator is fully symmetrical with a balanced input stage. Before irradiation (Pre-rad) the transresistance amplifier has a measured differential gain of 110 mV/4 fC, an average 10/90% rise time (t{sub 10/90%}) of 20 to 50 ns depending on the bias conditions, a noise figure of 433 {circle_plus} 93{center_dot}(C{sub t}){sup 1.08} and a power consumption of 750 {micro}W. The comparator uses bipolar transistors in the regenerative stage resulting in a small offset, a sensitivity <1.5 mV, and a power consumption of {approx}350 {micro}W at 40 MHz. The maximum pre-rad frequency at which the comparator is still functioning correctly is {approx}100 MHz. Pre-rad, the binary delay line has a delay of 2.1 {micro}s at 40 MHz and a power consumption of {approx}450 {micro}W/channel for a four-channel design. The complete readout channel--amplifier, comparator, and binary delay line--consumes {approx}1.5 mW. The entire readout system was implemented in the radiation-hard 0.8-{micro}m SOI-SIMOX BiCMOS-PJFET technology of DMILL.
- OSTI ID:
- 599825
- Journal Information:
- IEEE Journal of Solid-State Circuits, Journal Name: IEEE Journal of Solid-State Circuits Journal Issue: 1 Vol. 33; ISSN IJSCBC; ISSN 0018-9200
- Country of Publication:
- United States
- Language:
- English
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