Capacitance-measurement requirements and methods for VLSI

Thesis/Dissertation · Fri Jan 01 04:00:00 EST 1988

OSTI ID:5921589

Oristian, J E

Accurate capacitance models are essential for aggressive VLSI design. This study focuses on measurement methods that will produce accurate data upon which adequate models can be based. This work begins by reviewing the sources of capacitance associated with MOS integrated circuits. The transistor gate capacitances and extrinsic capacitances are shown to be the most significant capacitances in scaled technologies. The effects of probing parasitics on measurement accuracy are presented as a limitation to the size of capacitance that can be measured using standard off-chip techniques. Methods of minimizing the effects of probing capacitance that include proper sizing of test devices and using integrated electrostatic shielding are developed. A measurement technique which uses on-chip circuitry to eliminate the probing parasitics is presented. The details of the on-chip circuit design and the off-chip instrumentation required to support this measurement method are presented. It is shown in this development that the total source and drain capacitances are measured free of any parasitic using the on-chip method.

• Research Organization: Stanford Univ., CA (USA)
• OSTI ID: 5921589
• Country of Publication: United States
• Language: English

Related Subjects

42 ENGINEERING
426000 -- Engineering-- Components
Electron Devices & Circuits-- (1990-)
99 GENERAL AND MISCELLANEOUS
990200* -- Mathematics & Computers
CAPACITANCE
DESIGN
ELECTRICAL PROPERTIES
ELECTRONIC CIRCUITS
INTEGRATED CIRCUITS
MEASURING METHODS
MICROELECTRONIC CIRCUITS
MOS TRANSISTORS
PHYSICAL PROPERTIES
SCALE MODELS
SEMICONDUCTOR DEVICES
STRUCTURAL MODELS
TRANSISTORS