Status of the segment interconnect, cable segment ancillary logic, and the cable segment hybrid driver projects

Conference · Thu Aug 01 04:00:00 EDT 1985 · IEEE Trans. Nucl. Sci.; (United States)

OSTI ID:5886774

Swoboda, C; Barsotti, E; Chappa, S; Downing, R; Goeransson, G; Lensy, D; Moore, G; Rotolo, C; Urish, J

The FASTBUS Segment Interconnect (SI) provides a communication path between two otherwise independent, asynchronous bus segments. In particular, the Segment Interconnect links a backplane crate segment to a cable segment. All standard FASTBUS address and data transactions can be passed through the SI or any number of SIs and segments in a path. Thus systems of arbitrary connection complexity can be formed, allowing simultaneous independent processing, yet still permitting devices associated with one segment to be accessed from others. The model S1 Segment Interconnect and the Cable Segment Ancillary Logic covered in this report comply with all the mandatory features stated in the FASTBUS specification document DOE/ER-0189. A block diagram of the SI is shown.

• Research Organization: Fermi National Accelerator Lab., Batavia, IL
• OSTI ID: 5886774
• Report Number(s): CONF-850579-
• Conference Information: Journal Name: IEEE Trans. Nucl. Sci.; (United States) Journal Volume: NS-32:4
• Country of Publication: United States
• Language: English

Related Subjects

43 PARTICLE ACCELERATORS
430303* -- Particle Accelerators-- Experimental Facilities & Equipment
ACCELERATORS
COMMUNICATIONS
COMPUTERIZED CONTROL SYSTEMS
COMPUTERS
CONTROL SYSTEMS
CYCLIC ACCELERATORS
DATA ACQUISITION
DATA ACQUISITION SYSTEMS
DATA TRANSMISSION
ELECTRONIC CIRCUITS
ELECTRONIC EQUIPMENT
EQUIPMENT
EQUIPMENT INTERFACES
FASTBUS SYSTEM
FERMILAB ACCELERATOR
LOGIC CIRCUITS
NUCLEAR INSTRUMENT MODULES
PARALLEL PROCESSING
PROGRAMMING
SPECIFICATIONS
SYNCHROTRONS