On implementing large binary tree architectures in VLSI and WSI

Journal Article · Sat Apr 01 04:00:00 EST 1989 · IEEE Trans. Comput.; (United States)

DOI:https://doi.org/10.1109/12.21145· OSTI ID:5886371

Youn, H Y; Singh, A D

The complete binary tree is known to support the parallel execution of important algorithms, which has given rise to much interest in implementing such architectures in VLSI and WSI. For large trees, the classical H-tree layout approaches suffers from area inefficiency and long interconnects. Other proposed schemes are not well suited for the implementation of defect-tolerant designs. This paper presents an efficient scheme for the layout of large binary tree architectures by embedding the complete binary tree in a two-dimensional array of processing elements.

• Research Organization: 4751000; 4003000
• OSTI ID: 5886371
• Journal Information: IEEE Trans. Comput.; (United States), Journal Name: IEEE Trans. Comput.; (United States) Vol. 38:4; ISSN ITCOB
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990210* -- Supercomputers-- (1987-1989)
ALGORITHMS
COMPUTER ARCHITECTURE
COMPUTERS
DATA PROCESSING
DESIGN
DIGITAL COMPUTERS
ELECTRONIC CIRCUITS
FABRICATION
FAULT TOLERANT COMPUTERS
IMPLEMENTATION
INTEGRATED CIRCUITS
MATHEMATICAL LOGIC
MICROELECTRONIC CIRCUITS
PROCESSING
TWO-DIMENSIONAL CALCULATIONS