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A monolithic CMOS 16 channel, 12 bit, 10 microsecond analog-to-digital converter integrated circuit

Conference · · IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (United States)
OSTI ID:5869354
;  [1]
  1. Lawrence Berkeley Lab., CA (United States)
A monolithic CMOS 16 channel, 12 bit, 10 microsecond analog-to-digital converter has been designed and tested. The circuit converts 16 channels in parallel via a single slope ramp and Gray code counter algorithm. When biased for 10.0 us conversions of a 2 V input range into 4,050 voltage bins, and ohmically connected to a computer, initial testing shows typical performance is a noise level of 0.3 bis rms, integral non-linearity of 4 bins, adjacent channel crosstalk effects less than 1 bin, and total chip power consumption of 110 mW. The chip contains 16 sample and hold circuits, out of range logic, a Gray-to-binary converter, and tri-state data outputs for microprocessor compatibility. The die size is 4.4 by 1.5 mm in a 2 polysilicon, 1.2 micron feature size CMOS process, and has 52 bonding pads. Off Chip requirements are a single power supply, a single high speed clock, a precision voltage reference, three biasing resistors, and supply filtering capacitors. This custom circuit has advantages of lower power dissipation and less PC board area than competitive approaches, and is designed for further monolithic system integration. Design details and test results are presented.
DOE Contract Number:
AC03-76SF00098
OSTI ID:
5869354
Report Number(s):
CONF-921005--
Conference Information:
Journal Name: IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (United States) Journal Volume: 40:4 part 1
Country of Publication:
United States
Language:
English

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