Multiprocessor interrupt rerouting mechanism
Patent
·
OSTI ID:5805523
This patent describes a local area network (LAN) system having a computer system comprised of at least one bus, CPUs coupled to the bus for executing application processes, each CPU having a memory associated to it, the LAN also having at least one controller coupled to the bus and including at least one controller member, the LAN system further including resources coupled to the bus, and additional LANs coupled to at least one controller, and means for creating LAN control blocks (LCBs) within any of the memories, the LCBs for providing control information to effect the transfer of messages to/from the memories, resources, controller and LANs, the controller capable of effecting the interruption of any of the CPUs, a multiprocessor interrupt rerouting mechanism for rerouting messages intended for any one of the processors to a different one of the processors.
- Assignee:
- BULL HN Information Systems Inc., Billerica, MA
- Patent Number(s):
- US 4831518
- OSTI ID:
- 5805523
- Country of Publication:
- United States
- Language:
- English
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