Multiprocessing interrupt arrangement
Patent
·
OSTI ID:5255177
An interrupt system is described for use with each processor of a multiprocessor communication or telephone network, where one processor may request actions of another responding processor independent of the state of the other processors. The system consists of: means including a FIFO memory for queuing interrupt vector messages directed from a requesting processor to a particular other responding processor and received via the network directly from the requesting processor without intervention by any other processor, and means controlled only by the responding processor for sequentially providing to the directed processor an interrupt signal for each of the queued vector message.
- Assignee:
- AT and T Bell Labs., Murray Hill, NJ
- Patent Number(s):
- US 4604500
- OSTI ID:
- 5255177
- Country of Publication:
- United States
- Language:
- English
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