Bulldog: a compiler for VLIW architectures
Very Long Instruction Word architectures are reduced-instruction set machines with a large number of parallel, pipelined functional units but only a single thread of control. These machines offer the promise of an immediate order-of-magnitude speed-up for general-purpose scientific computing. But unlike previous machines such as the Cray and the FPS-164, it is impossible to program VLIW machines in machine language - only a compiler for a high-level language (Fortran.) makes these machines feasible. This thesis demonstrates, via a working compiler, that this symbiosis of new architecture and new compiling technology is practicable. A traditional compiler couldn't find enough parallelism in scientific programs to utilize a VLIW effectively. The Bulldog compiler uses several new compilation techniques: trace scheduling to find more parallelism, memory reference and memory bank disambiguation to increase memory bandwidth, and new code-generation algorithms. Results of preliminary experiments testing both the Bulldog compiler and various aspects of VLIW architectures are included.
- Research Organization:
- Yale Univ., New Haven, CT (USA)
- OSTI ID:
- 5724953
- Country of Publication:
- United States
- Language:
- English
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