A VLIW architecture for a trace scheduling compiler
Very long instruction word (VLIW) architectures were promised to deliver far more than the factor of two or three that current architectures achieve from overlapped execution. Using a new type of compiler which compacts ordinary sequential code into long instruction words, a large-scale VLIW machine was expected to provide from ten to thirty times the performance of a more conventional machine built of the same implementation technology. Multiflow Computer, Inc., has now built a VLIW called the TRACE along with its companion Trace Scheduling compacting compiler. This machine has three hardware configurations, capable of executing 7, 14, or 28 operations simultaneously. The ''seven-wide'' achieves a performance improvement of a factor or five or six for a wide range of scientific code, compared to machines of higher cost and faster chip implementation technology (such as the VAX 8700). The TRACE extends some basic reduced-instruction-set precepts: the architecture is load/store, the microarchitecture is exposed to the compiler, there is no microcode, and there is almost no hardware devoted to synchronization, arbitration, or interlocking of any kind (the compiler has sole responsibility for run-time resource usage). This paper discusses the design of this machine and presents some initial performance results.
- Research Organization:
- Multiflow Computer, Branford, CT (US)
- OSTI ID:
- 7061745
- Journal Information:
- IEEE Trans. Comput.; (United States), Journal Name: IEEE Trans. Comput.; (United States) Vol. 37:8; ISSN ITCOB
- Country of Publication:
- United States
- Language:
- English
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