Very long instruction word architectures and the ELI-512
Trace scheduling generates code for machines called very long instruction word architectures. In very long instruction word machines, many statically scheduled, tightly coupled, fine-grained operations execute in parallel within a single instruction stream. VLIWs are more parallel extensions of several current architectures. The author describes the ELI-512, which has a horizontal instruction word of over 500 bits and will do 10 to 30 RISC-level operations per cycle (Patterson 82). ELI stands for enormously longword instructions; 512 is the size of the instruction word it is hoped to achieve. (The current design has a 1200-bit instruction word.) Once it became clear that one could actually compile code for a VLIW machine, some new questions appeared, and answers are presented. How does one put enough tests in each cycle without making the machine too big. How does one put enough memory references in each cycle without making the machine too slow. 15 references.
- OSTI ID:
- 5290967
- Country of Publication:
- United States
- Language:
- English
Similar Records
Bulldog: a compiler for VLIW architectures
Measuring the parallelism available for very long instruction word architectures