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U.S. Department of Energy
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SCALX: A VLSI architecture for concurrent symbolic processing

Thesis/Dissertation ·
OSTI ID:5585552

A VLSI architecture intended for concurrent symbolic processing is presented. The approach starts with developing a hardware model for on-chip knowledge acquisition and works progressively towards the architectural basis. The model concepts, while formally conceived from neural network theory, do not target physiological modeling. Instead, the goal is to help develop autonomous systems that can make intelligent decisions on a real time basis. With this model, the knowledge is first represented by conceptual digraphs that in turn are stored into a reconfigurable perceptron-like network in which each node is a Boolean McCulloch-Pitts neuron. For on-chip knowledge representation, two methods are presented which directly map digraphs onto silicon. For inference, a computational approach is developed by which knowledge deduction and search processes are resorted to matrix and/or vector operations. A few algorithms which are specifically designed to implement the high speed search operations based on index-driven and value-driven systolic arrays are presented. These algorithms are analyzed in terms of time and space requirements. It is also shown that the index-driven systolic processing architecture can effectively solve the sparse matrix computation problem. Based on the computational model and the systolic design methodology, an array processor architecture suitable for VLSI implementation is developed. A hierarchical network simulator, encoded in C under VAX-8650, is also developed. This simulator is comprised of a conceptual digraph interpreter and a functional emulator for an application specific microprocessor, named SCALX 8900.

Research Organization:
Arizona State Univ., Tempe, AZ (United States)
OSTI ID:
5585552
Country of Publication:
United States
Language:
English