Development of a multi-level logic simulator for VLSI systems (including effects of delays, fanouts, and mixed level simulation)
The ongoing increase in the complexity of VLSI systems often requires simulation at different levels of abstraction i.e. process, transistor, gate, register transfer, structural, and behavioral level. For a system level design, it becomes quite tedious to maintain a simulation capability at each level, and further, to interface the results of one simulation level to another. To overcome these problems, a multi-level simulator is designed which is capable of simulating at any level of abstraction (gate level and above), and can also support mixed simulation i.e., simulating parts of a system at different levels of abstraction. The simulator has capabilities for a detailed simulation of a circuit including simulation of the effects of fanouts, delays, and different fabrication technologies. It also has an extensible structure so that user defined primitives can be added as the hardware becomes more complex. Efficiency with respect to time and storage becomes the most critical issue when designing such a complex simulation system. A timing wheel scheme based on event directed simulation (modified Ulrich's algorithm) is used to achieve higher time efficiency. Also, specially designed data structures improve the simulation time.
- Research Organization:
- Washington State Univ., Pullman (USA)
- OSTI ID:
- 5516610
- Resource Relation:
- Other Information: Thesis (Ph. D.)
- Country of Publication:
- United States
- Language:
- English
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