Multi-level logic array synthesis
Automatic synthesis of VLSI circuits from function descriptions creates the opportunity for vastly reduced design cost, but presents formidable challenges. This silicon compilation can be accomplished by a four step translation: (1) writing the function in terms of available logic components, (2) minimization of this logic representation, (3) mapping of logic into the target technology's circuit primitives, and (4) selection of a detailed layout configuration. Existing methods based on programmable logic array (PLA), standard cell and gate array topologies attack the problem using restrictions on logic minimization or circuit topology. A new method based on multilevel logic and Weinberger arrays integrates the entire compilation from functional description to layout generation, and provides greater flexibility in logic minimization, circuit topology, and design goals. Multi-level and Weinberger arrays serve as ideal partners in synthesis of large circuit structures. Deeply nested logic expressions can save area, power, and circuit delay compared to their more common sum-of-products equivalents, and Weinberger arrays can directly implement the arbitrary interconnections required by these complex logic functions. The Stanford Weinberger Array Minimizer and Implementor (SWAMI) system explores two phases of this compilation with special care, heuristic minimization of multi-level logic expressions, and gate placement in Weinberger arrays. SWAMI's logical optimization phase adopts heuristic methods to reduce the circuit area and delay for each logic function.
- Research Organization:
- Stanford Univ., CA (USA)
- OSTI ID:
- 5548801
- Country of Publication:
- United States
- Language:
- English
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