280-ps 6-bit RCJL decoder using high-drivability and unit circuit for a 1-kbit Josephson cache memory
A 6-bit resistor-coupled Josephson logic (RCJL) decoder has been developed for a 1-kbit Josephson cache memory. This decoder is an ac-powered latch decoder constructed in a parallel decoding architecture. The 6-bit decoder consists of three stages of AND gates and high-drivability OR gates, and direct-coupled inverters generating complement address signals. The decoder is designed to eliminate timing control signals for fast operation. The 6-bit decoder, consisting of 248 gates with 1042 Josephson junctions, was fabricated using Pb-alloy technology with 3.5-..mu..m minimum line-width patterns. A +- 11-percent gate-bias current margin was obtained. The shortest decoding time was 280 ps, including 66-ps signal propagation delay along the interconnecting strip line, with 4-mW power dissipation.
- Research Organization:
- Microelectronics Research Labs., NEC Corp., 1-1, Miyazaki Yonchome, Miyamae-ku, Kawasaki, Kanagawa 213
- OSTI ID:
- 5502192
- Journal Information:
- IEEE J. Solid-State Circuits; (United States), Journal Name: IEEE J. Solid-State Circuits; (United States) Vol. SC-22:5; ISSN IJSCB
- Country of Publication:
- United States
- Language:
- English
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Related Subjects
420800 -- Engineering-- Electronic Circuits & Devices-- (-1989)
99 GENERAL AND MISCELLANEOUS
990210* -- Supercomputers-- (1987-1989)
ALLOYS
ALTERNATING CURRENT
ARRAY PROCESSORS
COMPUTER ARCHITECTURE
CURRENTS
DATA PROCESSING
EFFICIENCY
ELECTRIC CURRENTS
ELECTRICAL EQUIPMENT
ELECTRONIC CIRCUITS
EQUIPMENT
FABRICATION
GATING CIRCUITS
INVERTERS
JOSEPHSON JUNCTIONS
JUNCTIONS
LEAD ALLOYS
LOGIC CIRCUITS
MEMORY DEVICES
PARALLEL PROCESSING
PROCESSING
PROGRAMMING
RESISTORS
SIGNAL CONDITIONING
SUPERCONDUCTING JUNCTIONS