Josephson 4 K-bit cache memory design for a prototype signal processor. III. Decoding, sensing, and timing

Journal Article · Sun Sep 15 00:00:00 EDT 1985 · J. Appl. Phys.; (United States)

DOI:https://doi.org/10.1063/1.336303· OSTI ID:5451434

Henkels, W H; Geppert, L M; Kadlec, J; Epperlein, P W; Beha, H; Chang, W H; Jaeckel, H

Designs for peripheral and timing circuits for a Josephson cache memory chip, organized as 1 K x 4-bits, are described. The designs were carried out employing a 2.5-..mu..m minimum-linewidth niobium edge-junction technology, in conjunction with the memory cell and driver array design described in the preceding companion paper. Significant changes in decoding, sensing, and timing, relating to widening operating margins over a predecessor all-Pb-alloy design are described in detail. The resultant nominal chip access time and power are, respectively, 970 ps and 10 mW.

• Research Organization: IBM Thomas J. Watson Research Center, Yorktown Heights, New York 10598
• OSTI ID: 5451434
• Journal Information: J. Appl. Phys.; (United States), Journal Name: J. Appl. Phys.; (United States) Vol. 58:6; ISSN JAPIA
• Country of Publication: United States
• Language: English

Related Subjects

420201* -- Engineering-- Cryogenic Equipment & Devices
71 CLASSICAL AND QUANTUM MECHANICS
GENERAL PHYSICS
ALLOYS
DATA PROCESSING
DESIGN
ELECTRONIC CIRCUITS
INTEGRATED CIRCUITS
JOSEPHSON JUNCTIONS
JUNCTIONS
LEAD ALLOYS
MEMORY DEVICES
MICROELECTRONIC CIRCUITS
NIOBIUM ALLOYS
PROCESSING
SUPERCONDUCTING JUNCTIONS
TIMING CIRCUITS