Josephson 4 K-bit cache memory design for a prototype signal processor. II. Cell array and drivers
A detailed optimized design of a 1 K-bit memory cell array with drivers and reset gates has been carried out based upon a set of projections for achievable tolerances in linewidths, resistances, and Josephson critical currents in a 2.5-..mu..m technology employing niobium edge junctions. The cell operating regions were significantly widened relative to a predecessor Pb-alloy design by adjusting gate and cell inductances, adjusting current levels, and by employing a different timing sequence for application of write controls. Much-improved control of array-line current oscillations, without loss of speed, was achieved by employing a distributed filtering scheme using distributed damping. The design employs trimming of currents to accommodate +- 8% chip-to-chip differences in the average critical current. The cell size is 63 x 63 ..mu..m. Monte Carlo calculations of threshold curve tolerances and operating current sensitivities and tolerances lead to a design-limited yield of about 95% for 4 K bits.
- Research Organization:
- IBM Thomas J. Watson Research Center, Yorktown Heights, New York 10598
- OSTI ID:
- 5369035
- Journal Information:
- J. Appl. Phys.; (United States), Journal Name: J. Appl. Phys.; (United States) Vol. 58:6; ISSN JAPIA
- Country of Publication:
- United States
- Language:
- English
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Related Subjects
71 CLASSICAL AND QUANTUM MECHANICS
GENERAL PHYSICS
ALLOYS
CRITICAL CURRENT
CURRENTS
DESIGN
ELECTRIC CURRENTS
ELECTRONIC CIRCUITS
FABRICATION
INTEGRATED CIRCUITS
JOSEPHSON JUNCTIONS
JUNCTIONS
LEAD ALLOYS
LINE WIDTHS
MEMORY DEVICES
MICROELECTRONIC CIRCUITS
MICROELECTRONICS
MONTE CARLO METHOD
NIOBIUM ALLOYS
OPERATION
OPTIMIZATION
OSCILLATIONS
SUPERCONDUCTING JUNCTIONS