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U.S. Department of Energy
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HgCdTe surface and defect study program. Interim technical Report No. 5, 31 December 1984-1 July 1985

Technical Report ·
OSTI ID:5498565
Correlations are made between capacitance-voltage measurements of MIS structures formed on horizontal zone-melt-grown HgCdTe (x = 0.3) wafers and the devices proximity to grain boundaries. Large changes in flat-band voltage and hysteresis are seen though the density of interface traps is relatively unaffected. The type and amount of changes seen are sufficient to account for the wafer-to-wafer inconsistencies often seen in C-V measurements. Similar fluctuations in surface properties over epitaxially grown wafers can be attributed to the low angle grain boundaries, which are present acting as undesired interfaces in a similar manner. Interface state structures for the HgCdTe PHOTOX SiO/sub 2/ interface was determined by complex admittance spectroscopy while compositional variations were measured by low-temperature (77k) electroreflectance. Results are also presented of the dependence of capacitance-voltage behavior on planar defect proximity. Deep states due to ion-implant damage were examined with DLTS and atomic profiles measured with SIMS are presented for A1, Mg, Na, Si, P, As, H, Br and Cu. Photoelectron-spectroscopy results are presented of the Ag/HgCdTe interface, e beam induced Hg desorption from a cleaved surface and of the surface that results from Br/sub 2/ based chemical treatments. Several recent theoretical studies of the local structure of semiconductor alloys are also presented.
Research Organization:
Santa Barbara Research Center, Goleta, CA (USA)
OSTI ID:
5498565
Report Number(s):
AD-A-166794/8/XAB
Country of Publication:
United States
Language:
English