Co-processor combination
A microprocessor system is described having means for inputting thereto an operating system which consists of: a first processor, a second processor, means intercoupling the first and second processors including an address bus and a data bus associated with the first processor and an address bus and a data bus associated with the second processor, a first memory associated with the first processor and coupled thereto via the first processor address bus and data bus, a second memory associated with the second processor and coupled thereto via the second processor address bus and data bus, a third memory associated with the first processor and comprising a read-only memory for storing a boot strap control program, power-up reset circuit means including means for generating a reset signal and means coupling the reset signal to the first processor causing first processor instruction operation in accordance with the boot strap control program to load the operating system into the first memory, means responsive to the program after loading of the operating system to terminate operation in accordance with the boot strap control program and commence operation in accordance with the operating system, means for reading the operating system to determine if the operating system is for 8-bit operation or 16-bit operation.
- Assignee:
- Tandy Corp., Fort Worth, TX
- Patent Number(s):
- US 4590556
- OSTI ID:
- 5480925
- Country of Publication:
- United States
- Language:
- English
Similar Records
Virtual memory cache for use in multi-processing systems
Hardware multiplier processor