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Triple modular redundancy for yield and reliability enhancement in integrated circuits

Thesis/Dissertation ·
OSTI ID:5480154
Redundancy is commonly used to enhance yield of integrated circuits. This research examines one type of redundancy (Triple Modular Redundancy-TMR) that can be used to improve both yield and reliability of ICs. In the past, TMR has been used to improve the reliability of electronic systems. When used for yield enhancement, many new issues arise related to modeling of the TMR ICs. This research improves existing models in two areas: compensating (or orthogonal) faults, and shared logic. Previous models are shown to be inadequate, and new models are developed that allow a time accuracy tradeoff. In addition, two design tools were written that can help the IC designer predict yield and reliability. The tools have a powerful predictive capability based on a statistical model of logic sharing that has been developed. The design tools were used to explore portions of the TMR IC design space such that guidelines were determined for designers using TMR for ICs.
Research Organization:
Carnegie-Mellon Univ., Pittsburgh, PA (USA)
OSTI ID:
5480154
Country of Publication:
United States
Language:
English