Novel approach to fault-tolerant logic and yield enhancement
Conference
·
OSTI ID:5257564
A design technique for improving reliability in function of a gate is proposed, in which a plurality of conventional logic circuits (gates) are used so as to give redundancy to a logic circuit itself. The gate with redundancy designed on the basis of the proposed technique is called the fault-tolerant gate (FTG) in this paper. The FTG has a recovery function with respect to a wider variety of faults. It is much more powerful than that offered by the TMR (triple modular redundancy) circuits. Therefore, the highly reliable logic circuits can be realized, and when the concept of FTGs is applied to vlsi chips the production yield must be enhanced. This paper is divided into three parts. In the first part, concrete methods to realize FTGs are described. The second part proves that the reliability of the gates can be improved by employing the concept of FTGs. In the last part, it is shown that the FTG contributes to the yield enhancement of vlsi chips. 13 references.
- OSTI ID:
- 5257564
- Country of Publication:
- United States
- Language:
- English
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