SPUR coprocessor interface description
Book
·
OSTI ID:5435704
This report describes the SPUR coprocessor interface. The interface provides enhanced performance potential by allowing parallel operations between the SPUR processor and SPUR coprocessors. A decoupled control and execution architecture allow data transfers to proceed while coprocessor functions are performed. Implicit and explicit synchronization mechanisms provide the programmer with complete control and flexibility. On-chip coprocessor register files and a wide data path between the memory and coprocessor minimize data transfer overhead. An intelligent interface control unit provides parallel decoding of instructions for maximum performance.
- OSTI ID:
- 5435704
- Country of Publication:
- United States
- Language:
- English
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Related Subjects
99 GENERAL AND MISCELLANEOUS
990210* -- Supercomputers-- (1987-1989)
ARRAY PROCESSORS
ARTIFICIAL INTELLIGENCE
COMMUNICATIONS
COMPUTER ARCHITECTURE
COMPUTERS
CONTROL EQUIPMENT
DATA TRANSMISSION
DIGITAL COMPUTERS
EFFICIENCY
EQUIPMENT
MEMORY DEVICES
PARALLEL PROCESSING
PROGRAMMING
SUPERCOMPUTERS
SYNCHRONIZATION
990210* -- Supercomputers-- (1987-1989)
ARRAY PROCESSORS
ARTIFICIAL INTELLIGENCE
COMMUNICATIONS
COMPUTER ARCHITECTURE
COMPUTERS
CONTROL EQUIPMENT
DATA TRANSMISSION
DIGITAL COMPUTERS
EFFICIENCY
EQUIPMENT
MEMORY DEVICES
PARALLEL PROCESSING
PROGRAMMING
SUPERCOMPUTERS
SYNCHRONIZATION