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Title: Improved method of preparing p-i-n junctions in amorphous silicon semiconductors

Patent ·
OSTI ID:5421009

A method of preparing p/sup +/-i-n/sup +/ junctions for amorphous silicon semiconductors includes depositing amorphous silicon on a thin layer of trivalent material, such as aluminum, indium, or gallium at a temperature in the range of 200/sup 0/C to 250/sup 0/C. At this temperature, the layer of trivalent material diffuses into the amorphous silicon to form a graded p/sup +/-i junction. A layer of n-type doped material is then deposited onto the intrinsic amorphous silicon layer in a conventional manner to finish forming the p/sup +/-i-n/sup +/ junction.

Research Organization:
Solar Energy Research Inst. (SERI), Golden, CO (United States)
DOE Contract Number:
AC02-83CH10093
Assignee:
Dept. of Energy
Application Number:
ON: DE85017736
OSTI ID:
5421009
Country of Publication:
United States
Language:
English