The Warp computer: Architecture, implementation, and performance

Journal Article · Tue Dec 01 04:00:00 EST 1987 · IEEE Trans. Comput.; (United States)

DOI:https://doi.org/10.1109/TC.1987.5009502· OSTI ID:5384793

Annaratone, M; Arnould, E; Gross, T; Kung, H T; Lam, M; Menzilcioglu, O; Webb, J A

The Warp machine is a systolic array computer of linearly connected cells, each of which is a programmable processor capable of performing 10 million floating-point operations per second (10 MFLOPS). A typical Warp array includes ten cells, thus having a peak computation rate of 100 MFLOPS. The Warp array can be extended to include more cells to accommodate applications capable of using the increased computational bandwidth. Warp is integrated as an attached processor into a Unix host system. Programs for Warp are written in a high-level language supported by an optimizing complier. This paper describes the architecture, implementation, and performance of the Warp machine. Each major architectural decision is discussed and evaluated with system, software, and application considerations. The programming model and tools developed for the machine are also described. The paper concludes with performance data for a large number of applications.

• Research Organization: Institute for Integrated Systems, ETH Zentrum, 8092 Zurich
• OSTI ID: 5384793
• Journal Information: IEEE Trans. Comput.; (United States), Journal Name: IEEE Trans. Comput.; (United States) Vol. C-36:12; ISSN ITCOB
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990210* -- Supercomputers-- (1987-1989)
ARRAY PROCESSORS
COMPUTER ARCHITECTURE
COMPUTER CODES
DATA PROCESSING
EXECUTIVE CODES
PERFORMANCE
PROCESSING