Systolic architectures based on barrel shifters for real-time digital signal processing
The throughput in real-time digital signal processing applications is limited by both the capability of the processors employed for number-crunching operations and the capacity of a supporting communications link. The systolic architectures eliminate the memory bandwidth problems by allowing multiple computations for each memory access and result in a speed-up in the execution time of compute-bound computations. However, the throughput rate in a systolic array is still limited by the computational time needed for one basic cell, which is composed of a multiplier and an accumulator. The multiplier in the basic cell requires either a large chip area if high speed is desired, or a large amount of time if serial architecture is used. The use of barrel shifters as computational elements in systolic arrays was proposed and studied in detail in this thesis. In the new systolic arrays there are two different structures, parallel and cascaded, that can be used to implement FIR filters. A unique cascaded structure was developed in this study that is shown to have better performance and requires significantly less basic cells.
- Research Organization:
- Cincinnati Univ., OH (USA)
- OSTI ID:
- 5569009
- Country of Publication:
- United States
- Language:
- English
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