Reconfigurable pipelined processor
This patent describes a reconfigurable pipelined processor for processing data. It comprises: a plurality of memory devices for storing bits of data; a plurality of arithmetic units for performing arithmetic functions with the data; cross bar means for connecting the memory devices with the arithmetic units for transferring data therebetween; at least one counter connected with the cross bar means for providing a source of addresses to the memory devices; at least one variable tick delay device connected with each of the memory devices and arithmetic units; and means for providing control bits to the variable tick delay device for variably controlling the input and output operations thereof to selectively delay the memory devices and arithmetic units to align the data for processing in a selected sequence.
- Assignee:
- Director of the National Security Agency, Washington, DC
- Patent Number(s):
- US 4858113
- Application Number:
- PPN: US 7038382A
- OSTI ID:
- 5347375
- Country of Publication:
- United States
- Language:
- English
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