Pulse-train residue arithmetic circuit using multiple-valued charge-coupled devices and its application to digital filter
A new design method for compact residue arithmetic circuit using multiple-valued charge-coupled devices (CCDS) is proposed. The multiple-valued ring counter for the residue arithmetic is designed by using the CCDS. Because the the structure of the counter is very simple, it is effectively used as the basic component to construct the residue arithmetic circuit. Modulo-m addition is performed by shifting the modulo-m multiple-valued ring counter, and coefficient multiplication is done by converting the multiple-valued code between the counters. The most important advantages of the proposed adder and multiplier are compact hardware and uniform operating time, so that these arithmetic circuits can be effectively employed in pipelining digital signal processing systems. Finally, it is demonstrated that the hardware complexity of the digital filter constructed with the quaternary logic ccds can be reduced to 70percent of that of the corresponding binary implementation. 13 references.
- OSTI ID:
- 5342328
- Country of Publication:
- United States
- Language:
- English
Similar Records
High-speed FIR digital filter using residue number arithmetic implemented in multiple-valued logic
Residue arithmetic circuit design based on integrated optics