Multiple-valued logic system synthesis and circuit design
Multiple-valued logic (MVL) systems hold the promise of a decrease in physical size and an increase in information processed per unit volume. With the advent of more sophisticated (VLSI) semiconductor technology, more and more attention has been paid to the MVL systems. This dissertation presents an in-depth fundamental study on the realization of MVL systems: System Synthesis and Circuit Design. After brief discussion on MVL systems in Chapter 1, a universal model on MVL systems is proposed in Chapter 2. Based on this generalized MVL system, most previous MVL systems can be deducted and extracted, and several new MVL systems of practical significance are developed. This Chapter also provides a general mathematical tool to prove their functional completeness. Chapter 3 defines some fresh concepts in MVL system synthesis. Based on this chapter theory, an effective computer algorithm is developed which facilitates the local minimization process. In chapter 4 a specific MVL system consisting of three primitives (Minimum, Literal and Modular Adder) is proposed. Its advantages are extended by developing MVL Programmable Logic Array (MVL PLA), MVL Carry Look-Ahead Technique and MVL sequential circuits. In Chapter 5 a quaternary Modular adder which is the most active core function in MVL systems is designed by using a new semiconductor technology - BI-CMOS process. The computer simulation results demonstrate its merit compared to other semiconductor technology.
- Research Organization:
- Boston Univ., MA (USA)
- OSTI ID:
- 5248830
- Resource Relation:
- Other Information: Thesis (Ph. D.)
- Country of Publication:
- United States
- Language:
- English
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