Self-checking VLSI building blocks for fault-tolerant multicomputers
Conference
·
OSTI ID:5198147
The use of self-checking nodes and links for implementing fault-tolerant VLSI multicomputers is proposed. The system consists of a large number of VLSI computers interconnected by high-speed dedicated links. Hardware which performs error detection is combined with system-level protocols which handle error recovery and fault treatment. The self-checking nodes notify the rest of the system when their output is erroneous. In order to achieve high fault coverage, error detection is accomplished by duplication and matching. The critical circuit in this scheme is a comparator, which must not be susceptible to faults which can remain undetected and later mask the failure of the functional modules. With both NMOS and CMOS technologies it is possible to implement a self-testing comparator which will produce an error indication if the comparator incurs any single physical defect. 13 references.
- OSTI ID:
- 5198147
- Country of Publication:
- United States
- Language:
- English
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