Fault tolerant VLSI multicomputers
Book
·
OSTI ID:5384601
An approach is presented to increase the reliability of future high-end systems beyond what is possible with technological solutions alone. The system consists of computation nodes and communication nodes, interconnected by high-speed dedicated links. These components are relied upon to detect errors while system level protocols are used for error recovery and reconfiguration. The use of duplication and matching for implementing the self-checking nodes allows us to restrict a detailed analysis of the impact of all possible faults to the comparator, a circuit that can be implemented in a relatively straightforward way in NMOS or CMOS technology.
- OSTI ID:
- 5384601
- Country of Publication:
- United States
- Language:
- English
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