Self-exercising in self-checking computer systems
Thesis/Dissertation
·
OSTI ID:6046085
Dormant faults and latent errors can accumulate in fault-tolerant computer systems and jeopardize detection and recovery procedures. This research proposes a design methodology, termed self-checking, self-exercising design, to rapidly expose and correct these conditions. This design methodology calls for interleaving short test cycles with the normal operation of a fault-tolerant computer. A hardware approach is developed to realize the methodology. Self-checking self-exercising design is illustrated by the design of three major components of a computer system: a memory, a processor data section, and a processor control unit. Special VLSI design techniques are employed to implement the self-checking self-exercising features. The methodology and some of the design techniques are evaluated for their effectiveness, practicality and performance. It is shown that the incremental cost of self-exercising is small in a system which already employs concurrent error detection, and that the self-exercising features can be quite effective.
- Research Organization:
- California Univ., Los Angeles, CA (USA)
- OSTI ID:
- 6046085
- Country of Publication:
- United States
- Language:
- English
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