Switch floor plants for restructurable VLSI/WSI
Thesis/Dissertation
·
OSTI ID:5180493
An electrically programmable switch has become a promising interconection technique for Restructurable VLSI/WSI systems because of its desirable properties, such as field reprogrammability, conventional fabrication technology and ease of changing the target architecture. However, the electrically programmable switch presents several problems to be solved, including long intermodule communication delay due to switches; the intermodule communication delay degrades VLSI/WSI system performance, particularly when it is a dominant factor in determining system speed. In this research, switch floor planning strategies (called switch floor plans) are proposed. The goal of those switch floor plans is to reduce the average intermodule communication delay and the total number of switches in the system. An ICT (Initial Configuration of Target architecture) design concept and the heterogeneous switch blocks over the target/host architecture are used to achieve such a goal. The ICT design is compared to other conventional-yield-enhancement methods by a combinatorial analysis. The proposed switch floor plans are evaluated by a computer simulation. Results show the desirability of the ICT design and the heterogeneous switches in the RVLSI/WSI system design.
- Research Organization:
- Minnesota Univ., Minneapolis (USA)
- OSTI ID:
- 5180493
- Country of Publication:
- United States
- Language:
- English
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