Interprocessor communication in a tightly coupled multiple processor architecture
Conference
·
OSTI ID:5169741
Communications between multiple processors in a tightly coupled, single common system bus architecture are discussed with attention to hardware aspects. A tightly coupled multiple processor architecture is first defined and then communication between processors is considered. After defining the needs of interprocessor communication, several means of communication are discussed. The most common means for passing messages is semaphores or mailboxes located in global resources or common access local resources. A second technique is through the common bus interrupt structure whereby processors may interrupt each other, and in turn, gain a response. Lastly, an external communications link is described such as a serial bus independent of the main data transfer bus. 2 references.
- OSTI ID:
- 5169741
- Country of Publication:
- United States
- Language:
- English
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