Interprocessor communication issues in fat-tree architectures

Technical Report · Tue Oct 01 04:00:00 EDT 1985

OSTI ID:6137749

In recent years, it has become increasingly evident that conventional computer architectures will be unable to perform, in an acceptable time frame, many of the computational functions that we would desire of them. Consequently, much research has been devoted to the concept of constructing supercomputers, which will be able to exploit the potential for parallel computation intrinsic to many large computational problems. Recently, Leiserson has proposed a multiprocessor scheme based on Leighton's tree of meshes, called a fat-tree. Conceptually, such a multiprocessor would be comprised of a set of n processing elements each situated as a leaf in a complete binary tree. Internal modes would be high speed switches which route messages being passed between processing elements, while edges between nodes would be bundles of constant bandwidth communication paths. This document addresses and defines some of the issues that effect interprocessor communication within a fat-tree multiprocessor. Specifically, it covers the following topics: (1) Addressing in a fat-tree; (2) Generation of addresses in a fat-tree; and (3) Allocation of communication resources in a fat-tree.

• Research Organization: Massachusetts Inst. of Tech., Cambridge (USA). Dept. of Electrical Engineering and Computer Science
• OSTI ID: 6137749
• Report Number(s): AD-A-163425/2/XAB
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990200* -- Mathematics & Computers
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ELECTRICAL EQUIPMENT
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MANAGEMENT
PARALLEL PROCESSING
PLANTS
PROGRAMMING
RESOURCE MANAGEMENT
SUPERCOMPUTERS
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