Layout techniques for integrated circuits
Several techniques are presented for solving circuit-layout problems. In particular, a channel-placement algorithm is first introduced to reduce the channel density (d) so that a channel router can complete the routing requirements in fewer tracks. A 4-layer channel-routing model is then formulated so that a general channel routing problem (CRP) with cyclic conflicts and long critical paths can be completed with d/2. Finally, the 4-layer, 2-dimensional switchbox routing problem needed to enhance the channel routing in general circuit layout is investigated from the graph-theoretical viewpoint. The channel-placement technique consists of two phases. Using the principle of decomposition, the initial placement phase effectively reduces the complexity of the problem and, therefore, improves the efficiency of the second phase, which is called the iterative improvement placement. The main feature of this phase is its hill-climbing ability to avoid being trapped at local minima. The combination of these two phases leads to an efficient technique for standard cell placement. To utilize multi-layer technology, a new 4-layer channel routing model is introduced to minimize the channel width of more-generalized CRP's. The 2-dimensional switchbox routing problem is transformed to an equivalent graph-theoretical problem.
- Research Organization:
- Texas Tech Univ., Lubbock (USA)
- OSTI ID:
- 5152181
- Country of Publication:
- United States
- Language:
- English
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