Some graph theoretic issues in VLSI design
Thesis/Dissertation
·
OSTI ID:5152027
This thesis investigates two problems in the domain of simulation and verification of large asynchronous circuits. The first one is the problem of detecting all bidirectional edges of a undirected graph, and arises naturally in the context of the simulation of an MOS transistor network. The second one is the problem of mechanically verifying the correctness of a large asynchronous circuit from its specifications presented in a propositional temporal logic of branching time. A related problem is to design an efficient algorithm to construct the Kripke Structure associated with the asynchronous circuit in a purely hierarchical manner and to study the natural sufficient conditions under which this is feasible. It is felt that the proposed research will be of interest to the practitioners in the field of VLSI design, since asynchronous circuits are prone to timing errors; and the importance of simulation and verification, particularly in this domain, can hardly be over-emphasized. In addition, the contribution of this research to the field of design and analysis of graph-theoretic algorithms, and to the field of verification of finite-state concurrent systems, may be of independent significance.
- Research Organization:
- Carnegie-Mellon Univ., Pittsburgh, PA (USA)
- OSTI ID:
- 5152027
- Country of Publication:
- United States
- Language:
- English
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