A CMOS signal conditioning ASIC for large silicon pixels
Conference
·
OSTI ID:513033
- IntraSpec, Inc., Oak Ridge, TN (United States)
- Oak Ridge National Lab., TN (United States)
We designed, constructed, and tested a CMOS ASIC consisting of a preamplifier, shaping amplifier, and externally adjustable discriminator. This device was designed for detectors with reasonably fast rise times (compared to 1 {mu}s) and capacitances in the range of 5 to 100 pF. The design was implemented with both PMOS and NMOS inputs. The NMOS version has a superior noise slope of 7 rms e/pF and an average noise at 6 pF input load of less than 375 rms electrons. The charge conversion sensitivity is 2.4 V/pC and the power drain is less than 10 mW/channel.
- OSTI ID:
- 513033
- Report Number(s):
- CONF-961123--
- Country of Publication:
- United States
- Language:
- English
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