Verification of timing constraints on large digital systems
A new approach to the verification of timing constraints on large digital systems has been developed. The associated algorithm is computationally efficient, and provides early and continuous feedback about the timing aspects of synchronous sequential circuits as they are designed. It also provides means for conveniently verifying the design section-by-section for designs that are too large to examine as a unit. This approach is new in that it uses a stable value to represent signals in the large majority of instances in which it is unnecessary to know whether the signals are true or false in order to examine satisfaction of the timing constraints. For the remaining instances, it represents the full value behavior of signals. This use of the stable value greatly reduces the number of states through which a digital system needs to be taken in the process of verifying its timing constraints. Not needing to know the values of most signals also greatly reduces the size of the data base needed to drive the verification process. Both of these savings are of exponential order. This approach thus makes feasible for the first time the exhaustive examination of complex digital circuits for satisfaction of timing constraints. A system has been implemented which takes a digital logic design specified in the SCALD Hardware Description Language, and verifies all of the timing constraints specified within it. This system has been used in the design of a very high-performance central processing unit, the S-1 Mark IIA processor. The use of the Timing Verifier allowed timing errors to be identified early in the design process. Such timely error elimination has permitted the design to be completed more rapidly, and has also supported the creation of a design which will perform more rapidly without timing errors, when it is implemented in hardware. 28 figures, 3 tables.
- Research Organization:
- California Univ., Livermore (USA). Lawrence Livermore National Lab.
- DOE Contract Number:
- W-7405-ENG-48
- OSTI ID:
- 5114864
- Report Number(s):
- UCRL-52995
- Country of Publication:
- United States
- Language:
- English
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Verification of timing constraints on large digital systems