Verification of timing constraints on large digital systems

Conference · Mon Apr 07 00:00:00 EST 1980

OSTI ID:6496513

McWilliams, T M

A new approach to the verification of the timing constraints on large digital systems has been developed. The associated algorithm is computationally very efficient, and provides early and continuous feedback about the timing aspects of synchronous sequential circuits as they are designed. It also provides means for conveniently verifying the design in sections, permitting the section-by-section timing verification of designs which are too large to examine as a unit on existing computer systems. A system using this algorithm has been implemented, and has been used to verify the timing constraints on the design of the S-1 Mark IIA processor.

• Research Organization: California Univ., Livermore (USA). Lawrence Livermore Lab.
• DOE Contract Number: W-7405-ENG-48
• OSTI ID: 6496513
• Report Number(s): UCRL-83791(Rev.1); CONF-800622-2(Rev.1)
• Resource Relation: Conference: 17. design automation conference, Minneapolis, MN, USA, 23 Jun 1980
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE
DIGITAL SYSTEMS
TIMING PROPERTIES
ALGORITHMS
AUTOMATION
TIMING CIRCUITS
ELECTRONIC CIRCUITS
MATHEMATICAL LOGIC
990200* - Mathematics & Computers