Triple-bus architecture gains speed, versatility

Journal Article · Wed Feb 01 04:00:00 EST 1984 · Comput. Des.; (United States)

OSTI ID:5108207

Cane, D; Mullen, S

In traditional minicomputer architecture, a single high speed internal bus transfers digital data throughout the system. Using multiple industry standard processors with multiple industry standard buses, the MC-500s 32-bit architecture distributes data acquisition, computation, and graphics tasks among several very high performance processors. The main system CPU uses a proprietary bus to connect the VLSI processors to system memory. A high performance Intel multibus (IEEE 796) supports a data acquistion and control processor (DA/CP), up to four independent graphics processors, and system peripherals. An enhanced std-bus-controlled by the DA/CP module-provides efficient data acquisition and control. This triple-bus design provides a flexible structure that anticipates future system enhancements with technological advances in microprocessors, memory, mass storage peripherals, communication devices, and realtime interfaces.

• Research Organization: Masscomputer, Littleton, MA
• OSTI ID: 5108207
• Journal Information: Comput. Des.; (United States), Journal Name: Comput. Des.; (United States) Vol. 2; ISSN CMPDA
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990200* -- Mathematics & Computers
COMMUNICATIONS
COMPUTERS
DATA ACQUISITION
DATA TRANSMISSION
DESIGN
EQUIPMENT INTERFACES