Lockup-free caches in high-performance multiprocessors
Journal Article
·
· Journal of Parallel and Distributed Computing; (United States)
OSTI ID:5001483
- Dept. of Electrical Engineering, Univ. of Southern California, Los Angeles, CA (US)
- Intel Corp., Santa Clara, CA (US)
The performance of shared-memory multiprocessors can suffer greatly from moderate cache miss rates because of the usually high ratio between memory access and cache access times. In this paper the authors propose a cache design in which the handling of one or several cache misses occurs concurrently with processor activity. Concurrent miss resolution in multiprocessor caches must function in conjunction with the system's synchronization hardware and cache coherence protocol. Through performance models, the authors identify system configurations for which concurrent miss resolution is effective. Compiler techniques to take advantage of the proposed design are illustrated at the end of the paper.
- OSTI ID:
- 5001483
- Journal Information:
- Journal of Parallel and Distributed Computing; (United States), Journal Name: Journal of Parallel and Distributed Computing; (United States) Vol. 11:1; ISSN JPDCE; ISSN 0743-7315
- Country of Publication:
- United States
- Language:
- English
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