The performance of software-managed multiprocessor caches on parallel numerical programs

Conference · Thu Jan 01 00:00:00 EST 1987

OSTI ID:5735099

Cheong, Hoichi; Veidenbaum, A V

In recent years interest has grown in multiprocessor architectures that can have several hundred processors sharing memory and all working on solving a single problem. Such multiprocessors are characterized by a long memory access time, which makes use of cache memories very important. However, the cache coherence problem makes the use of private caches difficult. The proposed solutions to the cache coherence problem are not suitable for a large-scale multiprocessor. We proposed a different solution that relies on a compiler to manage the caches during the execution of a parallel program. In this paper we discuss the performance evaluation of private cache memories for multiprocessors in general and present the results of performance improvement for parallel numerical programs using the caches managed with compiler assistance. The effect of cache organization and other system parameters such as cache block size, cache size, and the number of processors in the system performance is shown. 18 refs., 2 figs., 7 tabs.

• Research Organization: Illinois Univ., Urbana (USA). Center for Supercomputing Research and Development
• DOE Contract Number: FG02-85ER25001
• OSTI ID: 5735099
• Report Number(s): DOE/ER/25001-36; CONF-8706183-3; ON: DE88003590
• Resource Relation: Conference: ICS '87: international conference on supercomputing, Athens, Greece, 8 Jun 1987; Other Information: Paper copy only, copy does not permit microfiche production
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE
ARRAY PROCESSORS
MEMORY MANAGEMENT
PERFORMANCE TESTING
ALGORITHMS
BENCHMARKS
COMPUTER ARCHITECTURE
MATRICES
OPTIMIZATION
PARALLEL PROCESSING
TRANSLATORS
COMPUTER CODES
MATHEMATICAL LOGIC
PROGRAMMING
TESTING
990210* - Supercomputers- (1987-1989)