Design of an array processor for image processing

Journal Article · Fri Feb 01 04:00:00 EST 1991 · Journal of Parallel and Distributed Computing; (United States)

DOI:https://doi.org/10.1016/0743-7315(91)90122-P· OSTI ID:5001355

Lee, D L ^[1]

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1. Dept. of Computer Science, York Univ., North York, Ontario M3J 1P3 (CA)

This paper discusses the design of an array processor that permits parallel, conflict-free access and alignment of various N-vectors (e.g., rows, columns, contiguous blocks, and distributed blocks), for image processing. The ability to meet these requirements depends on skewing schemes for mapping an N {times} N array of image points into N parallel memories. The authors present an efficient nonlinear skewing scheme upon which the design of the array processor is based. The resulting array processor has the advantage of being both simple and efficient in two important aspects of the system. The addressing hardware for the parallel memories consists of O(log N) gates, and can calculate simultaneously N local addresses in O(1) time. Furthermore, the multistage interconnection network consists of O(N log N) gates and is able to align any of these vectors with a single pass through the network using the simplest control structure, namely, individual-stage control. Organization of the memory system is discussed, and construction of the interconnection network is given.

• OSTI ID: 5001355
• Journal Information: Journal of Parallel and Distributed Computing; (United States), Journal Name: Journal of Parallel and Distributed Computing; (United States) Vol. 11:2; ISSN 0743-7315; ISSN JPDCE
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990200* -- Mathematics & Computers
ARRAY PROCESSORS
COMPUTER ARCHITECTURE
COMPUTER CALCULATIONS
DESIGN
IMAGE PROCESSING
MEMORY MANAGEMENT
NONLINEAR PROBLEMS
PARALLEL PROCESSING
PROCESSING
PROGRAMMING