Multiprocessor interface
Journal Article
·
· IEEE Micro; (United States)
The author describes a hardware link between two microprocessor systems, each of which can be regarded as a peripheral of the other. The link uses two MC 68230 PI/T-parallel interface/timer-chips, one at each processor. Each PI/T interfaces to the high-speed bus signals coming from its processor, and to a shared TTL sequencer. The sequencer controls the transfer of data over a bidirectional data bus between the two PI/Ts, at a data rate optimized to the individual application. This interface is designed to allow the programmer a choice of data transfer control methods: software polling of a status register, either of two different interrupt request protocols, or DMA requests.
- Research Organization:
- Motorola Inc., Austin, TX
- OSTI ID:
- 5001048
- Journal Information:
- IEEE Micro; (United States), Vol. 4
- Country of Publication:
- United States
- Language:
- English
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