Prediction and measurement of temperature fields in silicon-on-insulator electronic circuits
- Stanford Univ., CA (United States)
- Behr GmbH & Co., Stuttgart (Germany)
- IBM Corp., Hopewell Junction, NY (United States)
- Massachusetts Institute of Technology, Cambridge, MA (United States)
Field-effect transistors (FETs) in conventional electron circuits are in contact with the high-thermal-conductivity substrate. In contrast, FETs in novel silicon-on-oxide (SOI) circuits are separated from the substrate by a thermally layer. The layer improves the electrical performance of SOI circuits. But it impedes conduction cooling of transistors and interconnects, degrading circuit reliability. This work develops a technique for measuring the channel temperature of SOI FETs. Data agree well with the predictions of an analytical thermal model. The channel and interconnect temperatures depend strongly on the device and silicon-dioxide layer thicknesses and the channel-interconnect separation. This research facilitates the thermal design of SOI FETs to improve circuit figures of merit, e.g., the median time to failure (MTF) of FET-interconnect contacts. 27 refs., 7 figs., 2 tabs.
- Sponsoring Organization:
- USDOE
- OSTI ID:
- 478458
- Journal Information:
- Journal of Heat Transfer, Journal Name: Journal of Heat Transfer Journal Issue: 3 Vol. 117; ISSN JHTRAO; ISSN 0022-1481
- Country of Publication:
- United States
- Language:
- English
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