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Robust Avalanche (1.5 kV, 2 kA/cm²) in Vertical GaN Diodes on Patterned Sapphire Substrate

Journal Article · · IEEE Electron Device Letters

The lack of avalanche capability is a key limitation of current lateral GaN devices. Despite the report of avalanche in vertical GaN-on-GaN devices, the high wafer cost hinders device commercialization. Here, in this work, we demonstrate a circuit-level avalanche in vertical GaN diodes on low-cost patterned sapphire substrate (PSS), with the avalanche voltage (1.57 kV) and avalanche current density (>2 kA/cm2) both being the highest reported in GaN devices on foreign substrates. The PSS enables a lower dislocation density than conventional sapphire substrate and is employed in high-voltage GaN devices for the first time. The avalanche voltage in the circuit test reaches 98% of the parallel-plane limit, further affirming that near-ideal avalanche breakdown can be realized on GaN devices on foreign substrates. These results show the promise of the GaN-on-PSS platform for low-cost, robust power devices.

Research Organization:
Oak Ridge National Laboratory (ORNL), Oak Ridge, TN (United States)
Sponsoring Organization:
USDOE Office of Science (SC), Basic Energy Sciences (BES). Scientific User Facilities (SUF)
Grant/Contract Number:
AC05-00OR22725
OSTI ID:
2573292
Journal Information:
IEEE Electron Device Letters, Journal Name: IEEE Electron Device Letters Journal Issue: 5 Vol. 46; ISSN 0741-3106; ISSN 1558-0563
Publisher:
IEEECopyright Statement
Country of Publication:
United States
Language:
English

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