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An integer-N frequency synthesizer for flexible on-chip clock generation

Journal Article · · Journal of Instrumentation

A low-power integer-N frequency synthesizer for flexible on-chip clock generation has been designed in a 65 nm CMOS process. The circuit can be programmed to generate two independent low-jitter clocks between 30 MHz and 3 GHz that are locked to a 10–50 MHz reference input. The design uses a phase-locked loop (PLL) with a dual-tuned LC voltage-controlled oscillator (VCO), programmable feedback divider, and dual output dividers. The total power consumption from 1.2 V and 0.8 V supplies is 4.0 mW. In conclusion, experimental results confirm the functionality of the proposed synthesizer over a wide range of output frequencies.

Research Organization:
Brookhaven National Laboratory (BNL), Upton, NY (United States)
Sponsoring Organization:
USDOE Office of Science (SC), Basic Energy Sciences (BES)
Grant/Contract Number:
SC0012704
OSTI ID:
2549225
Report Number(s):
BNL--227975-2025-JAAM
Journal Information:
Journal of Instrumentation, Journal Name: Journal of Instrumentation Journal Issue: 03 Vol. 20; ISSN 1748-0221
Publisher:
Institute of Physics (IOP)Copyright Statement
Country of Publication:
United States
Language:
English

References (9)

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DUNE as the Next-Generation Solar Neutrino Experiment journal September 2019
A PLL clock generator with 5 to 110 MHz of lock range for microprocessors journal November 1992
A filtering technique to lower LC oscillator phase noise journal January 2001
Testing of a Line Driver With Configurable Pre-Emphasis on Lossy Transmission Lines journal September 2024
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Analysis and Design of Power Supply Circuits for RF Oscillators journal December 2020
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